Flexible scan architecture

US7216274B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Talal K. Jaber · Austin, US
• Srinivas Patil · Austin, US
• Larry Edward Thatcher · Austin, US
• Chih-Jen Lin · Huizhou, CN
• Anil K. Sabbavarapu · Austin, US
• David M. Wu · Austin, US
• Madhukar Reddy · Carlsbad, US

Key dates

• Filing date: Jun 26, 2003
• Grant date: May 8, 2007
• Expiry date: Aug 25, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/2236
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.