Method of generating test patterns to efficiently screen inline resistance delay defects in complex ASICs
US7216280B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 27, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STE) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.