Pattern recognition in an integrated circuit design
US7216321B2 · kind B2 · utility
9Cited by
9References
37Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 23, 2004 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Apr 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for recognizing a pattern in a design of an integrated circuit (IC), comprising identifying a pattern correspondence element in a pattern instance. A pattern tree corresponding to the pattern instance is built. A list of candidate design correspondence elements in a design instance of the IC are built. Iteratively, for each design correspondence element in said list of candidate design correspondence elements each rank in a tree representation of said design instance built around said each design correspondence element is compared with corresponding rank in said pattern tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.