Voltage contrast test structure
US7217579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2002 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Mar 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N23/2258
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a defined scanning plane and operative, while in any one mechanical state, to scan a surface in the scanning plane within a two-dimensional scanning window, which has a given maximum size; (ii) providing in association with any layer of the wafer, it being a test layer, one or more test structures, each test structure including normally conductive areas within a normally non-conductive background in one or more layers, which include said test layer, the conductive areas formed as one or more patterns; the patterns in said test layer include one or more clusters of mutually isolated pads; each pad is conductively connected with a corresponding distinct point on the patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within a common window whose size does not exceed said maximum size of said scanning window; (iii) with said test layer forming the top surface of the wafer, placing the wafer on the SCPM and adjusting the mec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.