Method for manufacturing semiconductor device and electronic device and method for calculating connection condition
US7217645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2003 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solder is connected to the electrodes of the circuit board by using a temperature profile with a constant fusion temperature, a connection interface strength evaluation test is carried out on the soldered joints to obtain an appropriate reflow range free of decreases in the strength at the connection interface. On the basis of the appropriate reflow range obtained and using as the basis the chemical compound thickness which is determined uniquely by heat load, an appropriate reflow range in an optional temperature profile with one temperature peak is obtained. By carrying out connection in this appropriate reflow range, soldered joints can be obtained without decreases in the connection interface strength in the large-scale production stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.