Method and apparatus for locating and testing a chip
US7218128B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2005 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Feb 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0483
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A probe apparatus includes a nest element operable to precisely locate a chip having a plurality of exposed interconnects on a face of the chip to permit conductive connection to the chip through the interconnects. The nest element includes a pocket dimensioned to locate the chip within a tolerance of less than a width of one of the interconnects, and tapered walls extending upwardly and outwardly from the pocket, the tapered walls adapted to guide the chip into the pocket. One or more piezoelectric elements can be attached to or provided within to the nest element to impart vibration to the nest element, causing the chip to be “fluidized” such that the chip is guided into the pocket under the force of gravity or other externally applied force.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.