Physical realization of dynamic logic using parameterized tile partitioning
US7219326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Nov 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.