Apparatus and method to align clocks for repeatable system testing
US7221126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus using a clock generator with sequential logic to align the phase of a first clock generated on a receiving integrated circuit (IC) chip to a second clock received by the receiving IC chip. One embodiment of the invention involves a method for aligning the phase of a first clock relative to the phase of a second clock, wherein the first clock is provided by a clock generator in a data processing system. The method includes sampling the second clock with a sampling clock, detecting an edge on the second clock, and stretching the first clock to align the phase of the first clock relative to the phase of the second clock. A second embodiment of the invention involves a data processing system including a transmitting chip, a receiving chip, and a clock generator for aligning the phase of a first clock relative to the phase of a second clock, wherein the second clock is received by the receiving chip. The clock generator includes a sampling circuit to sample the second clock with a sampling clock, a circuit to detect an edge on the second clock, and a sequential logic circuit to stretch the first clock to align the phase of the first clock relative to the phase of …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.