Method and apparatus for memory block initialization
US7221185B1 · kind B1 · utility
3Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | May 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect of the invention, a circuit for generating addresses for memory initialization within a programmable logic device (PLD) is provided. The circuit includes input registers, which are loaded and unloaded with data triggered by the edge of a clock. The circuit further includes multiplexers, where the multiplexers are capable of receiving output of the input registers and encoded programmable addresses. The multiplexer generates encoded row addresses for a wordline of a memory within the PLD. The circuit includes a decoder to decode the encoded row addresses for the wordline of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.