Logic circuitry
US7221188B2 · kind B2 · utility
1Cited by
10References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Feb 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.