Circuit comparison by information loss matching
US7222317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2004 |
| Grant date | May 22, 2007 |
| Priority date | — |
| Expiry date | Mar 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.