Ferroelectric polymer memory with a thick interface layer
US7223613B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
According to one aspect of the invention, a memory array and a method of constructing a memory array are provided. An insulating layer is formed on a semiconductor substrate. A first metal stack is then formed on the insulating layer. The first metal stack is etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. The polymeric layer has a surface with a plurality of roughness formations. A second metal stack is formed on the polymeric layer with an interface layer, which is thicker than the heights of the roughness formations. Then the second metal stack is etched to form second metal lines. Memory cells are formed wherever a second metal line extends over a first metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.