Method for forming integrated advanced semiconductor device using sacrificial stress layer
US7223647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
Abstract
An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.