Methods of fabricating flash memory devices with floating gates that have reduced seams
US7223657B2 · kind B2 · utility
1Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | Sep 30, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Methods of fabricating a floating gate of a flash memory cell are provided in which a first polysilicon layer is formed between first and second isolation layers. An upper region of the first polysilicon layer is then oxidized. The oxidized upper region of the first polysilicon layer is subsequently removed. A second polysilicon layer is formed on the first polysilicon layer. The second polysilicon layer and the first polysilicon layer are patterned to form the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.