Device with integrated capacitance structure
US7224017B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Sep 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a device with integrated capacitance structure has at least one first and an adjacent second rewiring plane, each of which comprises at least one first partial structure and a second partial structure, which is different from the first partial structure, the second partial structure in each case substantially surrounding the first partial structure, and the first partial structure of the first rewiring plane being electrically connected to the second partial structure of the second rewiring plane and the second partial structure of the first rewiring plane being electrically connected to the first partial structure of the second rewiring plane and forming different poles of the capacitance structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.