Optical alignment loops for the wafer-level testing of optical and optoelectronic chips
US7224174B1 · kind B1 · utility
28Cited by
12References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4224
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of the wafer. A wafer level test system uses an optical probe to search for and align with an optical alignment loop. The test system uses a located alignment loop as a reference point to locate other devices on the wafer. The test system tests the operation of selected devices disposed on the wafer. The alignment loop is also used as a reference device for an adjacent device of unknown performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.