Circuit and method for testing semiconductor device
US7225379B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit includes: a register circuit, into which data is written after data is cleared in compliance with a reset instruction, the register circuit holding the written data until a subsequent reset instruction is input; a TAP controller which receives a signal for selecting a test mode, and writes the data into the register circuit in accordance with the signal for selecting a test mode in synchronization with a first clock; a pattern generation circuit which generates a test pattern in accordance with the data held in the register circuit, and outputs data based on the test pattern to the circuit to be tested in synchronization with a second clock; and a data comparator which receives data output from the circuit to be tested in synchronization with the second clock, and makes an evaluation of performance in accordance with the test pattern and the data output from the circuit to be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.