Methods for modeling latch transparency
US7225419B2 · kind B2 · utility
4Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.