Clock tree distribution generation by determining allowed placement regions for clocked elements
US7225421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2005 |
| Grant date | May 29, 2007 |
| Priority date | — |
| Expiry date | Aug 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.