High-pressure processing chamber for a semiconductor wafer
US7225820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Jul 14, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S134/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing chamber having an improved sealing means is disclosed. The processing chamber comprises a lower element, an upper element, and a seal energizer. The seal energizer is configured to maintain the upper element against the lower element to maintain a processing volume. The seal energizer is further configured to generate a sealing pressure in a seal-energizing cavity that varies non-linearly with a processing pressure generated within the processing volume. In one embodiment, the seal energizer is configured to minimize a non-negative net force against one of the upper element and the lower element above a threshold value. The net force follows the equation P2*A2−P1*A1, where P2 equals the sealing pressure, P1 equals the processing pressure, A2 equals a cross-sectional area of the seal-energizing cavity, and A1 equals a cross-sectional area of the processing volume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.