Method and system for a pad structure for use with a semiconductor package
US7227260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/924
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.