Memory devices with page buffer having dual registers and method of using the same
US7227785B2 · kind B2 · utility
4Cited by
25References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2005 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Nov 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.