Patent · US Expired

Clock data recovery circuitry associated with programmable logic device circuitry

US7227918B2 · kind B2 · utility

38Cited by

62References

138Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Edward Aung · San Leandro, US
Henry Y. Lui · San Jose, US
Paul Butler · Methuen, US
John E. Turner · Beaverton, US
Rakesh Patel · Cupertino, US
Chong H. Lee · San Ramon, US

Key dates

Filing date	Mar 13, 2001
Grant date	Jun 5, 2007
Priority date	—
Expiry date	May 1, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0337
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.