System and method for maintaining cache coherency in a shared memory system
US7228389B2 · kind B2 · utility
8Cited by
61References
6Claims
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Key dates
| Filing date | Dec 20, 2005 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Dec 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.