Lock caching for compound atomic operations on shared memory
US7228391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for lock caching for compound atomic operations (i.e. a read or write operation to more than one 4-byte word) on shared memory is provided. In a computer system including a memory shared among a plurality of processing entities, for example, multiple threads, a method of performing compound atomic operations comprises providing a pool of locks for synchronizing access to the memory; assigning the locks among the plurality of entities to minimize lock contention; and performing the compound atomic operations using the assigned locks. Each lock may be assigned in accordance with an address of the shared memory from the processing entity's compound atomic operations. Assigning locks may be performed in a manner to minimize concurrent atomic updates to the same or overlapping portions of the shared memory. For example, the addresses of the memory from the compound atomic operations may be aliased in accordance with a known upper bound on the amount of the shared memory that may be affected by any atomic operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.