Raul E. Silvera
52Patents
7h-index
52Co-inventors
71Inventor score
Filing activity: Jun 8, 2004 → Aug 13, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7487501B2 | Distributed counter and centralized sensor in barrier wait synchronization | Physics | 20 | Active |
| US7228391B2 | Lock caching for compound atomic operations on shared memory | Physics | 18 | Expired |
| US8161464B2 | Compiling source code | Physics | 16 | Active |
| US7856628B2 | Method for simplifying compiler-generated software code | Physics | 12 | Active |
| US8015556B2 | Efficient method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations | Physics | 9 | Active |
| US8104030B2 | Mechanism to restrict parallelization of loops | Physics | 9 | Active |
| US7856627B2 | Method of SIMD-ization through data reshaping, padding, and alignment | Physics | 8 | Active |
| US9286190B2 | Inserting implicit sequence points into computer program code to support debug operations | Physics | 7 | Active |
| US8146070B2 | Method and apparatus for optimizing software program using inter-procedural strength reduction | Physics | 7 | Active |
| US7555748B2 | Method and apparatus for improving data cache performance using inter-procedural strength reduction of global objects | Physics | 7 | Active |
| US7487497B2 | Method and system for auto parallelization of zero-trip loops through induction variable substitution | Physics | 6 | Active |
| US9274931B2 | Inserting implicit sequence points into computer program code to support debug operations | Physics | 6 | Active |
| US8037462B2 | Framework for parallelizing general reduction | Physics | 6 | Active |
| US8423750B2 | Hardware assist thread for increasing code parallelism | Physics | 5 | Active |
| US8332833B2 | Procedure control descriptor-based code specialization for context sensitive memory disambiguation | Physics | 5 | Active |
| US8640113B2 | setjmp/longjmp for speculative execution frameworks | Physics | 5 | Active |
| US9569127B2 | Computer instructions for limiting access violation reporting when accessing strings and similar data structures | Physics | 4 | Active |
| US8117604B2 | Architecture cloning for power PC processors | Physics | 3 | Active |
| US8375375B2 | Auto parallelization of zero-trip loops through the induction variable substitution | Physics | 3 | Active |
| US8056066B2 | Method and apparatus for address taken refinement using control flow information | Physics | 3 | Active |
| US9298630B2 | Optimizing memory bandwidth consumption using data splitting with software caching | Physics | 3 | Active |
| US9104577B2 | Optimizing memory bandwidth consumption using data splitting with software caching | Physics | 3 | Active |
| US8191057B2 | Systems, methods, and computer products for compiler support for aggressive safe load speculation | Physics | 3 | Active |
| US7472382B2 | Method for optimizing software program using inter-procedural strength reduction | Physics | 2 | Active |
| US8341615B2 | Single instruction multiple data (SIMD) code generation for parallel loops using versioning and scheduling | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.