Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation
US7228515B2 · kind B2 · utility
6Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2004 |
| Grant date | Jun 5, 2007 |
| Priority date | — |
| Expiry date | Mar 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.