Process for manufacturing dual work function metal gates in a microelectronics device
US7229873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.