Self-aligned double gate device and method for forming same
US7230270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Jan 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.