Purge-based floating body memory

US7230846B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ali Keshavarzi · Portland, US
• Stephen H. Tang · Pleasanton, US
• Dinesh Somasekhar · Hillsboro, US
• Fabrice Paillet · Hillsboro, US
• Muhammad M. Khellah · Lake Oswego, US
• Yibin Ye · Portland, US
• Vivek K. De · Beaverton, US
• Gerhard Schrom · Hillsboro, US

Key dates

• Filing date: Jun 14, 2005
• Grant date: Jun 12, 2007
• Expiry date: Aug 30, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2211/4016
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.