Method of forming a locally strained transistor
US7232730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
Abstract
A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.