Three-dimensional memory device incorporating segmented bit line memory array
US7233024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | May 21, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/91
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.