Integrated semiconductor product with metal-insulator-metal capacitor

US7233053B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Klaus-Peter Koller · Bad Soden, DE
• Heinrich Körner · Bogen, DE
• Michael Schrenk · Dießen am Ammersee, DE

Key dates

• Filing date: Jun 10, 2004
• Grant date: Jun 19, 2007
• Expiry date: Sep 22, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76838
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.