Semiconductor arrangement
US7233059B2 · kind B2 · utility
0Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Aug 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.