Circuitry for eliminating false lock in delay-locked loops
US7233182B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Aug 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay-locked loop (DLL) acquires correct lock when the delay line on the DLL delays a reference signal by one clock period. False lock occurs when the delay line delays the reference signal by more than one clock period. False lock may be detected by a false lock detector. The false lock detector may include (1) flip-flops to take samples of the delay line outputs and (2) combinational logic for detecting patterns in the samples that may indicate false lock. Once false lock has been detected, a hold circuit may ensure that false lock persists for at least the amount of time required by the DLL to acquire lock (i.e., to prevent reset of the DLL before it has acquired lock). After this determination is made, a reset generator may produce a reset signal for resetting the DLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.