Methods and apparatus for reducing power consumption in a processor using clock signal control
US7233188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Feb 2, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus provide for: producing a control signal at a first substantially steady state logic level indicative of a sleep mode, and at a second substantially steady state logic level indicative of a normal mode; producing a gate signal that is at a substantially steady state null level when the control signal is at the first logic level, and that oscillates at a local clock frequency when the control signal is at the second logic level; producing a local clock signal from a system clock signal as a function of the gate signal; and interposing at least one signal propagation latch circuit between an origin of the control signal and the location at which the gate signal is produced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.