System for erasing nonvolatile memory
US7233529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Aug 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.