Method for controlling data output timing of memory device and device therefor
US7233533B2 · kind B2 · utility
12Cited by
1References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jun 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a device for controlling data output of a memory device using a DLL clock signal, the device comprising: an output driver for outputting data; and a CAS latency control unit for generating a signal adjusting an operation timing of the output driver depending on CAS latency, wherein the CAS latency control unit generates a signal for controlling the output driver by using time difference between the DLL clock signal and an external clock applied to the memory device from an exterior.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.