Memory mapped Input/Output operations
US7234037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with the definition(s) of the z/Architecture; and wherein a process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.