Variable clocked scan test circuitry and method
US7234092B2 · kind B2 · utility
4Cited by
15References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.