Transistor with silicon and carbon layer in the channel region
US7235822B2 · kind B2 · utility
150Cited by
29References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2005 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Dec 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor and method of manufacturing thereof having stressed material layers formed in the channel to increase the speed and improve performance of the transistor. A layer of silicon and carbon is epitaxially grown in the channel region. A thin semiconductor material may be formed over the layer of silicon and carbon, and a stressed semiconductor layer may be epitaxially grown prior to forming the layer of silicon and carbon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.