Defect monitor for semiconductor manufacturing capable of performing analog resistance measurements
US7235994B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Jan 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.