Fast bistable circuit protected against random events
US7236031B2 · kind B2 · utility
0Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2005 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Aug 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.