Precharge arrangement for read access for integrated nonvolatile memories
US7236403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.