Configurable out-of-order data transfer in a coprocessor interface
US7237090B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.