Method and apparatus for reducing timing pessimism during static timing analysis
US7237212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Dec 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies a set of worst-case violating paths using the region-specific derating factors. Next, the system computes path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data and the path properties. Finally, the system identifies zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.