Methods for fabricating one or more metal damascene structures in a semiconductor wafer
US7238614B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating one or more metal (e.g., copper) damascene structures in a semiconductor wafer use at least three polishing steps to reduce erosion topography in the resulting metal damascene structures and/or increase throughput. The polishing steps may be performed at four polishing units of a polishing apparatus, which may include one or more pivotable load/unload cups to transfer the semiconductor wafer between some of the polishing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.