Voltage tolerant protection circuit for input buffer
US7239176B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2005 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Sep 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved voltage tolerant protection circuit for input buffer comprising a transmission gate circuit receiving input from the pad for passing the input signal to the input of the input buffer, a control signal generator electrically coupled between the transmission gate circuit and the pad to provide a control signal for operating the transmission gate circuit, and an N-Well generation circuit electrically coupled between the pad and the transmission gate circuit, and also electrically coupled to the control signal generator for generating a bias signal for the transmission gate circuit and the control signal generator. Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors, minimizes power supply consumption and transfers signals without any change in amplitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.