Asynchronous system-on-a-chip interconnect
US7239669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2003 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Mar 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13362
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.