Area efficient BIST system for memories
US7240255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design for Test Assist Logic (DAL) block. The DAL associated with any particular memory array recognizes commands from the BIST that are for the associated memory array, controls the execution of write/read commands for the associated array and sends data read from the memory array along with appropriate commands to the comparator after a latency that is appropriate for the associated array Thus, there are standardized commands from the BIST, but each DAL executes these commands in a manner appropriate for the memory array (or arrays) associated with the particular DAL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.